发表论文
(1) COMPACT: Co-processor for Multi-mode Precision-adjustable Non-linear Activation Functions, DATE, 2023, 第 3 作者(2) Context-Enhanced Stereo Transformer, European Conference on Computer Vision(ECCV), 2022, 第 4 作者(3) An Intelligent Real-Time Object Detection System on Drones, APPLIED SCIENCES-BASEL, 2022, 通讯作者(4) Energy-Efficient Inference for Recurrent Neural Networks in Edge-Cloud Computing, Symmetry-Basel, 2022, 第 3 作者(5) LIPFD-NPU: Low-Overhead Instruction-Driven Permanent Fault Detection for Neural Processing Unit, 2022 VTC-FALL workshop, 2022, 第 2 作者(6) 多模态高精度非线性激活函数协处理器设计, 计算机辅助设计与图形学学报, 2022, 第 2 作者(7) AnchorCapsule: a datastream-serving post-processor for object detection in embedded vision SoC, Ieee Transactions on Circuits and Systems Ii-Express Briefs, 2022, 通讯作者(8) Improving system latency of AI accelerator with on-chip pipelined activation preprocessing and multi-mode batch inference, IEEE 3RD INTERNATIONAL CONFERENCE ON ARTIFICIAL INTELLIGENCE CIRCUITS AND SYSTEMS (AICAS), 2021, 通讯作者(9) CNN-DMA: A predictable and scalable direct memory access engine for convolutional neural network with sliding-window filtering, ACM Great Lakes Symposium on VLSI (GLSVLSI), 2021, 通讯作者(10) OR-ML: Enhancing Reliability for Machine Learning Accelerator with Opportunistic Redundancy, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021, 通讯作者(11) Long exposure convolutional memory network for accurate estimation of finger kinematics from surface electromyographic signals, JOURNAL OF NEURAL ENGINEERING, 2021, 第 3 作者(12) Highly-accurate gesture recognition based on ResNet with low-budget data gloves, International Conference on Advanced Information Science and System (AISS 2021), 2021, 第 6 作者(13) Accelerating Atrous Convolution with Fetch-and-Jump Architecture for Activation Positioning, IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA), 2020, 通讯作者(14) Accelerating hybrid and compact neural networks targeting perception and control domains with coarse-grained dataflow reconfiguration, Accelerating hybrid and compact neural networks targeting perception and control domains with coarse-grained dataflow reconfiguration, 半导体学报:英文版, 2020, 通讯作者(15) Learn to Make Decision with Small Data for Autonomous Driving: Deep Gaussian Process and Feedback Control, JOURNAL OF ADVANCED TRANSPORTATION, 2020, 第 7 作者(16) Improving the Performance of Whale Optimization Algorithm through OpenCL-Based FPGA Accelerator, COMPLEXITY, 2020, 第 4 作者(17) A Current Mirror Cross Bar Based 2.86-TOPS/W Machine Learner and PUF with < 2.5% BER in 65nm CMOS for IoT Application, 2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2019, 第 2 作者(18) A Torque Observer for IPMSM Drives Based on Deep Neural Network, PROCEEDINGS OF THE 2019 14TH IEEE CONFERENCE ON INDUSTRIAL ELECTRONICS AND APPLICATIONS (ICIEA 2019), 2019, 第 6 作者(19) Accelerating Compact Convolutional Neural Networks with Multi-threaded Data Streaming, 2019 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI 2019), 2019, 通讯作者(20) A Generic Block-Level Error Confinement Technique for Memory Based on Principal Component Analysis, APPLIED SCIENCES, 2019, 第 3 作者(21) A 2.86-TOPS/W Current Mirror Cross-Bar-Based Machine-Learning and Physical Unclonable Function Engine For Internet-of-Things Applications, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2019, 第 2 作者(22) Current Mirror Array: A Novel Circuit Topology for Combining Physical Unclonable Function and Machine Learning, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2018, 第 1 作者(23) Low-cost vector map assisted navigation strategy for autonomous vehicle, 2018 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2018), 2018, 通讯作者(24) 基于可重构阵列架构的强化学习计算引擎, 集成技术, 2018, 第 2 作者(25) A CGRA based Neural Network Inference Engine for Deep Reinforcement Learning, 2018 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2018), 2018, 通讯作者(26) Accelerator Design for Convolutional Neural Network with Vertical Data Streaming, 2018 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2018), 2018, 通讯作者(27) 一种基于轻量级矢量地图的无人车导航方法, 集成技术, 2018, 第 2 作者(28) Automated High-level Modeling of Power, Temperature and Timing Variation for Microprocessor, KMUTNB: International Journal of Applied Science and Technology, 2017, 第 1 作者(29) Currentmirrorarray: AnovellightweightstrongPUFtopologywithenhancedreliability, 2017, 第 1 作者(30) Reliable Many-Core System-on-Chip Design using K-Node Fault Tolerant Graphs, 2016 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), 2016, 通讯作者(31) A Low Overhead Error Confinement Method based on Application Statistical Characteristics, PROCEEDINGS OF THE 2016 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2016, 通讯作者(32) Mitigation of NBTI-induced Timing Degradation in Processor, ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2016, 第 1 作者(33) Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance, 2016 ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2016, 第 2 作者(34) Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control, 25th IEEE Asian Test Symposium (ATS), 2016, 第 1 作者(35) Architectural Reliability Estimation using Design Diversity, PROCEEDINGS OF THE SIXTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2015), 2015, 通讯作者(36) Architectural Error Prediction using Probabilistic Error Masking Matrices, PROCEEDINGS OF THE SIXTH ASIA SYMPOSIUM ON QUALITY ELECTRONIC DESIGN ASQED 2015, 2015, 通讯作者(37) Processor Design with Asymmetric Reliability, 2014 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), 2014, 通讯作者(38) System-level Reliability Exploration Framework for Heterogeneous MPSoC, GLSVLSI'14: PROCEEDINGS OF THE 2014 GREAT LAKES SYMPOSIUM ON VLSI, 2014, 通讯作者(39) Power Modeling and Estimation during ADL-driven Embedded Processor Design, 2013 4TH ANNUAL INTERNATIONAL CONFERENCE ON ENERGY AWARE COMPUTING SYSTEMS AND APPLICATIONS (ICEAC), 2013, 通讯作者(40) Fast Reliability Exploration for Embedded Processors via High-level Fault Injection, PROCEEDINGS OF THE FOURTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2013), 2013, 通讯作者(41) Opportunistic Redundancy for Improving Reliability of Embedded Processors, 2013 8TH INTERNATIONAL DESIGN AND TEST SYMPOSIUM (IDT), 2013, 通讯作者(42) Accurate and efficient reliability estimation techniques during ADL-driven embedded processor design, Design, Automation, and Test in Europe (DATE), 2013, 第 1 作者(43) High-Level Design Space and Flexibility Exploration for Adaptive, Energy-Efficient WCDMA Channel Estimation Architectures, HINDAWI PUBLISHING CORPORATION, 2012, 第 3 作者(44) ASIC synthesis using architecture description language, Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012, 第 1 作者(45) Adaptive energy-efficient architecture for wcdma channel estimation, International Conference on Reconfigurable Computing and FPGAs, 2011, 第 1 作者