Dr.-Ing. Zheng Wang, PhD supervisor


Research Areas

Computer architecture, VLSI design, Electronic Design Automation (EDA), embedded system


2010.09--2015.10 RWTH-Aachen University, Germany. Doctor of Engineering (Dr.-Ing.) in Electrical Engineering and Information System

2007.10--2009.09 Technische Universität München (TUM), Germany.  Master of Science (M. Sc.) in Communication Electronics

2002.09--2007.07 Shanghai Jiao Tong University (SJTU), China. Bachelor of Science (B. Sc.) in Applied Physics


15 years of hands-on developing and research experience in computer architecture, design of Very Large System Integration (VLSI) and Electronic Design Automation (EDA). Industrial experience in Infineon AG, Germany. 

Currently I am working in following areas:

1. Problem modeling, data analysis, software, architecture and circuits co-design for machine learning applications with successful ASIC tape-outs/FPGA prototyping as well as tool flow construction

2. Design space exploration of micro-architecture using high-level processor description language with cycle-accurate simulator and RTL generation.

Linkedin site:

Google scholar site:

Work Experience

2020.01-now Associate professor, Shenzhen Institute of Advanced Technology (SIAT), Chinese Academy of Sciences

2017.01-2019.12 Assistant professor, Shenzhen Institute of Advanced Technology (SIAT), Chinese Academy of Sciences

2015.10-2016.12 PostDoc reseacher, Nanyang Technological University (NTU), Singapore

Teaching Experience
Master-level course "Computer Architecture and Digital System" Fall, 2021


(1) Improving System Latency of AI Accelerator with on-Chip Pipelined Activation Preprocessing and multi-Mode Batch Inference, IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2021, 第 2 作者
(2) OR-ML: Enhancing Reliability for Machine Learning Accelerator with Opportunistic Redundancy, Design, Automation and Test in Europe (DATE), 2021, 第 2 作者
(3) Long Exposure Convolutional Memory Network for accurate estimation of finger kinematics from surface electromyographic signals, Journal of Neural Engineering, 2021, 第 3 作者
(4) CNN-DMA: A predictable and scalable direct memory access engine for convolutional neural network with sliding-window filtering, ACM Great Lakes Symposium on VLSI (GLSVLSI), 2021, 第 1 作者
(5) Accelerating hybrid and compact neural networks targeting perception and control domains with coarse-grained data-flow reconfiguration, Journal of Semiconductors, 2020, 第 1 作者
(6) Improving the performance of whale optimization algorithm through OpenCL-based FPGA accelerator, Hindawi Complexity, 2020, 第 4 作者
(7) Accelerating Atrous Convolution with Fetch-and-Jump Architecture for Activation Positioning, IEEE International Conference on Integrated Circuits, Technologies & Applications, 2020, 第 2 作者
(8) Learn to Make Decision with Small Data for Autonomous Driving: Deep Gaussian Process and Feedback Control, Hindawi Journal of Advanced Transportation, 2020, 第 7 作者
(9) A Generic Block-level Error Confinement Technique for Memory based on Principal Component Analysis, Applied Sciences, 2019, 通讯作者
(10) A 2.86-TOPS/W Current Mirror Cross-Bar Based Machine-Learning and Physical Unclonable Function Engine for Internet-of-Things Applications, IEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 第 2 作者
(11) Accelerating Compact Convolutional Neural Networks with Multi-threaded Data Streaming, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2019, 通讯作者
(12) A Current Mirror Cross Bar Based 2.86-Tops/W Machine Learner and PUF with <2.5% BER in 65nm CMOS for IoT Application, IEEE International Symposium on Circuits and Systems (ISCAS), 2019, 第 2 作者
(13) A Torque Observer for IPMSM Drives Based on Deep Neural Network, IEEE Conference on Industrial Electronics and Applications, 2019, 第 5 作者
(14) 基于可重构阵列架构的强化学习计算引擎, 集成技术, 2018, 通讯作者
(15) 一种基于轻量级矢量地图的无人车导航方法, 集成技术, 2018, 通讯作者
(16) Current Mirror Array: A Novel Circuit Topology for Combining Physical Unclonable Function and Machine Learning, IEEE Transactions on Circuits and Systems I: Regular Papers, 2018, 第 1 作者
(17) Detecting Fault Injection Attacks Based on Compressed Sensing and Integer Linear Programming, IEEE Transactions on Dependable and Secure Computing, 2018, 第 3 作者
(18) Accelerator design for convolutional neural network with vertical data streaming, IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2018, 通讯作者
(19) A CGRA based Neural Network Inference Engine for Deep Reinforcement Learning, IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2018, 通讯作者
(20) Low-cost vector map assisted navigation strategy for autonomous vehicle, IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2018, 通讯作者
(21) Current Mirror Array: a Novel Lightweight Strong PUF Topology with Enhanced Reliability, IEEE International Symposium on Circuits and Systems (ISCAS), 2017, 第 1 作者
(22) Automated High-level Modeling of Power, Temperature and Timing Variation for Microprocessor, KMUTNB: International Journal of Applied Science and Technology, 2017, 第 1 作者
(23) Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control, 25th IEEE Asian Test Symposium (ATS), 2016, 第 3 作者
(24) Reliable Many-Core System-on-Chip Design using K-Node Fault Tolerant Graphs, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016, 第 1 作者
(25) Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance, Design Automation Conference (DAC), 2016, 第 2 作者
(26) A Low Overhead Error Confinement Method based on Application Statistical Characteristics, Design, Automation, and Test in Europe (DATE), 2016, 第 1 作者
(27) Mitigation of NBTI-induced Timing Degradation in Processor, ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2016, 第 3 作者
(28) Architectural Error Prediction using Probabilistic Error Masking Matrices, Asia Symposium on Quality Electronic Design (ASQED), 2015, 第 1 作者
(29) Architectural Reliability Estimation using Design Diversity, International Symposium on Quality Electronic Design (ISQED), 2015, 第 1 作者
(30) Processor design with asymmetric reliability, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2014, 第 1 作者
(31) System-level reliability exploration framework for heterogeneous MPSoC, ACM proceedings of the 24th edition of the great lakes symposium on VLSI (GLSVLSI), 2014, 第 1 作者
(32) Opportunistic redundancy for improving reliability of embedded processors, 8th International Design and Test Symposium (IDT), 2013, 第 1 作者
(33) Accurate and efficient reliability estimation techniques during ADL-driven embedded processor design, Design, Automation, and Test in Europe (DATE), 2013, 第 1 作者
(34) Power Modeling and Estimation during ADL-driven Embedded Processor Design, 4th Annual International Conference on Energy Aware Computing Systems and Applications (ICEAC), 2013, 第 1 作者
(35) Fast reliability exploration for embedded processors via high-level fault injection, International Symposium on Quality Electronic Design (ISQED), 2013, 第 1 作者
(36) ASIC synthesis using architecture description language, Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012, 第 1 作者
(37) High-level design space and flexibility exploration for adaptive, energy-efficient WCDMA channel estimation architectures, International Journal of Reconfigurable Computing, 2012, 第 2 作者
(38) Adaptive energy-efficient architecture for wcdma channel estimation, International Conference on Reconfigurable Computing and FPGAs, 2011, 第 2 作者



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